With reference to FIG. 1, cache memory 102 (which may be referred to herein simply as “cache”) is memory (typically fast memory) that is configured to store a subset of the data stored in a main memory 104 to reduce the time for a device 106 (e.g. a central processing unit (CPU)) to access the data stored in the main memory. When the device 106 (e.g. CPU) wants to access a specific memory address of the main memory 104 the device 106 first looks in the cache 102. If the cache 102 contains data associated with the specific memory address then there is a cache hit and the data is quickly and directly supplied to the device 106 from the cache 102. If, however, the cache 102 does not contain data associated with the specific memory address then there is a cache miss and a time-consuming read of the main memory 104 is performed. The data read from the main memory 104 is then stored in the cache 102 so that the data is available to a subsequent access of the specific memory address.
An integrated circuit hardware design for a cache memory is typically verified before hardware is generated according to the integrated circuit hardware design. Generally integrated circuit hardware designs for cache memory are verified using dynamic simulation-based verification in which a random set of input stimuli are applied to an instantiation of the integrated circuit hardware design and the output is compared to a known reference output. However, it is difficult, using random input stimuli, to verify that the instantiation of the integrated circuit hardware design handles the corner cases (e.g. infrequently occurring scenarios) as expected. This is particularly true for more complex cache memories, such as n-way set associative cache memories.
The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known methods and systems for verifying a hardware design for a cache memory.